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What does this print, #2
I meant to post more of these, but here’s one for fun: class A(object): def __eq__(self, rhs): return True class B(object): def __eq__(self, rhs): return False print A() in [B()] print B() in [A()] Maybe not quite as surprising once you see the results and think about it, but getting this wrong was the source…
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Stack vs Register bytecodes for Python
There seems to be a consensus that register bytecodes are superior to stack bytecodes. I don’t quite know how to cite “common knowledge”, but doing a google search for “Python register VM” or “stack vs register vm” supports the fact that many people believe this. There was a comment on this blog to this effect as well.…
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Why is Python slow
In case you missed it, Marius recently wrote a post on the Pyston blog about our baseline JIT tier. Our baseline JIT sits between our interpreter tier and our LLVM JIT tier, providing better speed than the interpreter tier but lower startup overhead than the LLVM tier. There’s been some discussion over on Hacker News, and the discussion…
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Benchmarking: minimum vs average
I’ve seen this question come up a couple times, most recently on the python-dev mailing list. When you want to benchmark something, you naturally want to run the workload multiple times. But what is the best way to aggregate the multiple measurements? The two common ways are to take the minimum of them, and to…
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Xilinx Zynq: Initial Impressions
I’ve been passively watching the FPGA space for the past few years. Partially because I think they’re a really interesting technology, but also because, as The Next Platform says: [T]here are clear signs that the FPGA is set to become a compelling acceleration story over the next few years. From the relatively recent Intel acquisition…
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Pyston 0.4 released!
I haven’t been very active on this blog since I’ve been busy with Pyston — and we just released version 0.4, check it out on the Pyston blog!
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What’s happening on Pyston
People sometimes ask me how Pyston is going and what we’re currently working on. It’s a bit hard to answer, both because we haven’t had a release recently with some headline-worthy features, but also because a lot of the stuff we’re working on is individually pretty small. Sometimes I try to find some sort of way…
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Quick report: Altera vs Xilinx for hobbyists
I’ve done a number of projects involving Xilinx FPGAs and CPLDs, and honestly I’m frustrated with them enough to be interested in trying out one of their competitors. This is pretty rant-y, so take it with a grain of salt but some of my gripes include: Simply awful toolchain support. The standard approach is to…
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Impressed
I remarked to a friend recently that technology seems to increase our expectations faster than it can meet them: “why can’t my pocket-computer get more than 6 hours of battery life” would have seemed like such a surreal complaint 10 years ago. For that reason I want to recognize an experience I had lately that…
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Getting started with STM32 microcontrollers
I was excited to see recently that ARM announced their new Cortex-M7 microcontroller core, and that ST announced their line using that core, the STM32F7. I had briefly played around with the STM32 before, and I talked about how I was going to start using it — I never followed up on that post, but I got…