Conservation Cores (ASPLOS ’10)

I read (part of) an interesting paper today out of UCSD.  The main premise of the paper is that “the rate at which we can switch transistors is far outpacing our ability to dissipate the heat created by those transistors.”  The rest of paper is then devoted to describing a system they have of determining energy-intensive parts of the application, and then running them directly on hardware to make them more energy efficient.

I don’t have any experience in this area so I don’t know how to evaluate their proposed design, but I found the premise very interesting (and I would assume that anyone knowledgeable of the field would find it very unsurprising).  I never really thought about how the first order design constraint on a chip is the power budget that it has, not so much the size or other physical properties.  Apparently only 7% of a chip can be run at full frequency at any given time (I’m not sure exactly what that means, ie what “full frequency” is), which is very surprising to me.  It seems so…wasteful, that there is so much potential power in the silicon, but we can’t use all of it because of heat constraints.

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