The current state of the Bitcoin mining world seems to revolve around new ASIC-based miners that are coming out, such as from Butterfly Labs.  These devices seem to be very profitable investments if you can get your hands on one — this calculator says that the $2,499 50GH/s machine should pay itself off itself off in 35 days.  This made me start thinking that with such high margins for the end-user, the manufacturing costs must be low enough that even at a multiple of them, it should be possible to do this yourself in a way that could be close enough to profitable that the educational value justifies the cost.

So, out of curiosity, I decided to look into how feasible it would be to produce actual ASICs.  From doing some google searching, people seem to say that it starts at multiple hundreds of thousands of dollars, though other people say that it can be cheaper using “multi-wafer fabrication”.

Multi-wafer fabrication

Multi-wafer fabrication is where an intermediary company collects orders from smaller customers, and batches them into a single order for the foundry.  My friend pointed me to mosis.com, which offers MWF and has an automated quote system, so I asked for a quote for their cheapest process, GlobalFoundries 0.35um CMOS.  The results were pretty surprising:

• You order in lots of 50 chips
• Each lot costs $320 per mm^2, with a minimum size of 0.06mm^2 ($20 total!) and maximum of 9mm^2.
  • For the other processes that I checked, additional lots are significantly cheaper than the first one
• Your packaging options are either $3000 for all lots for a plastic QFN/QFP package, or $30-$70 per chip for other types

So the absolute minimum cost seems to be $50, if you want a single 250um-by-250um chip in the cheapest package (a ceramic DIP28).  You probably want a few copies, so let’s make that about $100 — this is cheap enough that I would do it even if it serves no practical purpose.

Die size estimation

The huge question, of course, is what can you actually get with a 0.06mm^2 chip?  I tried to do a back-of-the-envelope calculation:

• Xilinx claims that each Logic Cell is worth 15 “ASIC Gates”; they only say this for their 7-series fpgas, which may have different cells than my Spartan 6, and this is their marketing material so it can only be an overestimate, but both of these factors will lead to a more conservative estimate so I’ll accept their 15 number
• The Spartan 6 LX16 has 14,579 logic cells (again, I’m not sure why they decided to call it the “16”); let’s assume that I’m fully utilizing all of them as 15 ASIC gates, giving 218,685 gates I need to fit on the ASIC.
• This page has some info on how to estimate the size of an asic based on the process and design:
  • For a 3 metal-layer, 0.35um process, the “Standard-cell density” is approximately 16k gates per mm^2
  • The “Gate-array utilization” is 80-90%, ie the amount of the underlying standard cells that you use
  • The “Routing factor” (ie 1 + routing_overhead) is between 1.0 and 2.0
  • This gives an effective gate density of between 6k and 14k gates per mm^2… much less than I thought.

So if we’re optimistic and say that we’ll get the 14k gates/mm^2, and that my design actually requires fewer than 218k gates, it’s possible that my current 5MH/s circuit could fit in this process.  There are many other processes available that I’m sure get much higher gate densities — for example, this thread says that a TSMC 0.18um, 7LM (7 layer metal) process gets ~109k gates/mm^2, and using the InCyte Chip Estimator Starter Edition says that a 200k-gate design will take roughly 4mm^2 on an “Industry Average” 8LM 0.13um process.

Feasibility

So if I wanted to translate my current design, I’m looking at a minimum initial cost of $3,000; I’m sure this is tiny compared to a commercial ASIC, but for a “let’s just see if I can do it” project, it’s pretty steep.

On the other end of the spectrum, what if I’m just interested in profitability as a bitcoin miner?  Let’s say that I get the DIP28 packages and I can somehow use all 50; this brings the price up to $4,500.  To determine how much hashing power I’d need to recoup that cost, I turned to the bitcoin calculator again; I gave it a “profitability decline per year” of 0.01, meaning that in one year the machine will produce only 1% as much money, which I hope is sufficiently conservative.  Ignoring power costs, the calculator says I’ll eventually earn one dollar for every 9MH/s or so of computational power: assuming I’m able to optimize my design up to 10MH/s, getting 500MH/s from 50 chips is only worth $50 or so.  I’m starting to think something is very wrong here: either I can get a vastly more powerful ASIC to fit in this size, or more likely, these small prototyping batches will never be cost-competitive with volume-produced ASICs.

So, just for fun, let’s look at the high end: let’s create a 5mm x 5mm (max size) chip using TSMC’s 65nm process, and order 2 lots of 100.  Chip Estimator says that we could get maybe 7.2M gates on this thing, so getting 200 of these chips provides about 150x more power than 50 200k chips.  The quote, however, is for $200k, so to break even I’d need to get 2TH/s from these chips, or 10GH/s per chip; with space for 150 of my current hashing cores, I’d need to get 65MH/s per core, which is far beyond where I think I can push it.

To try to get a sense of how much of the discrepancy is because I can get more power per gate vs how much is because of prototyping costs, let’s just look at the cost for the second lot of that order: $12k.  This means each chip costs $150 once you include packaging, so I would have to get 1.5GH/s out of it, or 10MH/s per core, which is only twice as much as I’m currently getting.  The 10x price difference between the first and second lots makes it definitely seem like the key factor is how much volume you can get.

That said, if I wanted to create a single hashing-core chip for fun, it looks like I could get a couple of those for under $1,000.

Other costs

One big cost that’s unknown to me is the cost of the design software you need to design an ASIC in the first place.  I assume that this is in the $10,000+ range, which again is out of my price range, though the silver lining is that you “only” have to pay this cost once.  Another cost that I haven’t mentioned is the cost of the board to actually get this running; if I’m optimizing for cost, though, I think getting a simple, low-pin-count package (like the DIP28) shouldn’t be too costly to build a board for.

My overall take from this is that the minimum cost for a custom ASIC is extremely low ($100), but making anything of a reasonable size is still going to start you off over $10,000.