This is part 3 of my Building a Processor series, where I try to build a processor on an FPGA board.  This post is about getting the seven-segment display to work.

Previous: first circuit.

This post is going to be pretty short; there are many great resources out there that give step-by-step descriptions for building the circuitry for this, so I’m going to focus on how it fits into the broader picture.  You can see an MIT lab assignment for doing this (exercise 8), which is part of the MIT 6.111 OpenCourseWare course, and if you want to skip to the results you can check out my github.

So, the goal for this post is to get the seven-segment display working.  Having the leds is great and I’ll definitely be using them in the future, but I want more output than the leds provide.  This “seven-segment display” actually has eight segments per digit, so in theory we could display 32 bits of information with it, as opposed to the 8 with the leds, though we’re going to trade off amount of information for readability, and only use 16 out of the 64 (32 without the dot) combinations per digit, the ones that correspond to hex characters.

The thing that makes this tricky is the design of the display seems peculiar, at least at first: it has 8 pins for each of the 8 segments, and then 4 more pins for “character enable” signals.  So the display is only capable of showing the same pattern on all digits at once, though you can select which digits to display it on.  It seems like the common thing to do is iterate very quickly over the four digits, and for each digit enable just that digit and show the corresponding segments; if we switch quickly enough between the digits, the human eye won’t be able to tell that this is happening.  So my seven-segment circuit will have the following:

• A counter that keeps track of time, so we can know which digit to display
• A mapping from 4-bit binary values to 8-bit lcd segment masks
• A selector that selects the appropriate 4 bits from the 16-bit input, maps it to the corresponding output, and enables the right digit.

More practically, I’m also going to:

• Create a new file to put this new “sseg” module in
• Add the “clk” input to my board and uncomment the line in the ucf file
• Have the sseg module take a parameter that determines the switching frequency
• Pick a divisor that scales the 100MHz input clock to roughly 1ms per digit

You can see the final result at this github tag.