This is part 4 of my Building a Processor series, where I try to build a processor on an FPGA board.  This post is about using a DCM to manage the clock frequency.

Previous: seven-segment display.

In the previous post, I created a simple driver for the display, which uses the externally-provided clock to count time.  The Nexys 3 comes with a 100MHz oscillator, provided at the “clk” input pin, but the Spartan 6 includes a number of Digital Clock Managers (DCMs) that allow us to modify and transform the input clock signal in various ways.  I don’t even know all the things that can be done with it, but the most important feature to me is that it has the ability to take one clock signal and output a different signal at a different frequency.  I’m going to use this to create a slower 10MHz clock so that I don’t have to worry about efficiency at this stage.

Warning: it’s possible to do this with a simple circuit that counts to 10 and then resets, but this is a bad idea!  I learned this the hard way: the DCM is some specialized hardware that is specifically designed for this task, and will generate clean transitions, and will use special “low-skew clock networks” on the chip to distribute the resulting signal.  I don’t know everything that goes into making it special (I think the core generator also knows how to pick values that minimize jitter?), but it’s definitely a Bad Thing to try to do this yourself.

One thing I had to learn when getting started in digital design, is that the industry loves to refer to reusable modules as “IP cores”, or just “cores” when it won’t be confused with something else.  It seems like this usually means that one company will license some of their IP, in the form of a reusable “core”, for others to use.  This actually seems like a pretty neat idea, since you can go and leverage someone else’s work and use a pre-made DDR or PCI express module.  In ISE, Xilinx takes this one step further, where they have a “Core Generator”, which will generate a custom IP core for you based on your requirements.

This Core Generator is also how Xilinx gives you the ability to create modules that are custom-tailored to your device: we’re going to use the Core Generator to produce a DCM “core” that we can stick into the FPGA.  A DCM core (ie the code to use a DCM) is pretty simple and we could easily build one by hand, but to play it safe I’m going to use the Core Generator, even though it’s painfully slow.  The steps I took are:

• Project->New Source, then selected “IP (CORE Generator & Architecture Wizard)”, and gave it the filename “dcm”.  I left it in the ipcore_dir since this process will end up generating a huge number of files.
• Waited while it was “Creating a selector for specified hardware…”
• Checked “Only IP compatible with chosen part”, and searched for “clock”, and picked the Clocking Wizard, pressed Next and Finish.
• The first time, I tried turning off Phase Alignment since I thought it’d be an unnecessary feature, but ISE started complaining to me about how the clocks have no relation to each other, so I turned it back on.
• On the next page set the Requested Frequency to 10MHz, and said thit it should drive a BUFG.
• On the next page, turned off the optional inputs; hit next twice; on page 5 change the names to just CLK_IN and CLK_OUT; press Next then Generate.

You can get a lot more information about the Clocking Wizard in Xilinx’s documentation for it, or check out my results here.  (Note: it’s much harder to understand the result of this part since it’s all in auto-generated files that aren’t designed to be human-readable.)

One annoying thing to note is that the DCM generator produces verilog code that the synthesizer (XST) will emit warnings for; I had to manually edit the ipcore_dir/dcm.v file and remove the unused locked_int and status_int wires, and the corresponding links to the outputs of the DCM_SP module; this will probably get reverted if I ever modify the DCM parameters.  diff