As the title suggests, I successfully reflowed my first BGA chips today. I followed the seemingly-easy steps from the last post, and the board correctly enumerated! In a decent bit of thinking ahead, I not only connected the JTAG pins to the header, but I also paired up all CPLD IOs so that I could do some pin-level testing as well. I created a simple JTAG test file which toggled each pin one by one (side note: it’s interesting to read about how one can reduce the number of test patterns, though I didn’t care too much), and verified that all the patterns worked! This means that on this board, the 32 IO pins were all connected exactly to the other pin they were supposed to. I suppose it could have been luck, and I have tons of miraculously-benign shorts…
Flush with success I reflowed another board. And this time it came out obviously misaligned. I hooked up the tester anyway, and yes it indeed failed to enumerate.
So then I tried a third board, being much more careful about the alignment: as I mentioned in a previous post, it really does work well to simply push the chip down firmly and slide it around until it locks into the PCB. I had wussed out on doing that for the second chip, but I went through with it for the third one. So it went into the toaster oven, and came out looking good — and got confirmed by the tester that the JTAG circuit worked and all 32 IOs were connected.
I feel like this is an interesting conclusion: in two out of the three tests all pins soldered correctly, and the third test was completely non-functional. I take this to mean that BGA yield issues take place largely at the chip level, rather than the ball level. I didn’t test a whole lot of balls — only 64 IO balls and maybe 16 power and JTAG balls, compared to 300-some on an FPGA, but so far so good.
I’m not sure where to go from here: the goal was to do BGA FPGAs, but I’m currently stuck getting a QFP FPGA to work so I’ll have to hold off on that. The big increase in number of balls is pretty daunting, though the CPLDs I tested on were 0.5mm-pitch whereas the parts I’ll actually be working with will be 0.8mm or 1.0mm, which hopefully gives some extra process tolerance.